Heterogeneous Integration Paves the Way for the Future of HPC and Hyperscale Computing

Wednesday, July 13, 2022

2:00pm – 4:45pm

Location: TechTALKS Stage, South Hall, Lower Lobby

Sponsored by

Session Moderator(s)

William Chen, PhD

Chair
Heterogeneous Integration Roadmap, IEEE EPS

Speaker(s)

Lori Diachin, PhD

Deputy Director
Exascale Computing Project (ECP), CA, United States
John Shalf, MS

Department Head for Computer Science
Lawrence Berkeley National Laboratory / Applied Mathematics and Computational Science / Department of Energy, CA, United States

Panel Session Moderator(s)

Ravi Mahajan, PhD

Intel Fellow, Director of Pathfinding for Assembly and Packaging Technologies for 7nm Silicon and Beyond , Technology and Manufacturing Group
Intel, Arizona, United States
WB

W.R. Bill Bottoms

Chairman
Third Millennium Test Solutions

Panelist(s)

Bapi Vinnakota

OCP Open Domain-Specific Architecture Project Lead
Open Compute Project Foundation
Gabriel Loh, PhD

Senior Fellow
AMD
Jie Xue, Ph.D

VP
Cisco, CA, United States
Madhu Iyengar, PhD

Principal Engineer
Google, California, United States
Philip Wong, PhD

Willard R. and Inez Kerr Bell Professor
School of Engineering
Stanford University, CA, United States

Co-hosted by the Electronic Packaging Society (EPS) of IEEE and the SEMI Americas Advanced Packaging Committee.

Heterogeneous Integration through advanced packaging innovations is widely acknowledged as being increasingly important to drive performance, system availability, power efficiency, cost and time to market of microelectronics systems, from HPC & Data Centers, to 5G & Beyond, mobile, automotive, IoT, medical and health markets.

As the full microelectronics design and manufacturing supply chain come together to respond to challenges and develop new solutions, two integration technologies, in particular, are paving the way to make these innovations possible – System in Package (SiP) and Chiplets Integration. HPC systems have adopted the mantra of co-design at the system-level to address waning performance gains from shrinking transistors. By co-designing in a system-application approach, innovators across the whole ecosystem will deliver the next extension of Moore’s law in the next 25 years.

This Heterogeneous Integration session takes a full ecosystem approach to look at how advanced packaging in SiP and Chiplets are paving the way for the Future of HPC and Hyperscale computing. Two DoE Supercomputers coming online this year - Frontier at Oak Ridge National Lab, and Aurora at Argonne National Lab – will be the premier case studies of this historic switch to Heterogeneous Integration at the Exascale computing level. Together they illustrate the vast potential of Heterogeneous Integration to unleash the power of semiconductors and microelectronics innovations for the benefit of humanity.

Presentations:

2:00pm – 2:10pm

Session Introduction and Welcome Remarks
Session Moderator: William Chen, PhD – Heterogeneous Integration Roadmap, IEEE EPS
2:10pm – 2:35pm

Powering HPC Discoveries through New Developments in the Exascale Computing Project
Speaker: Lori Diachin, PhD – Exascale Computing Project (ECP)
2:35pm – 3:00pm

Heterogeneous Integration for HPC
Speaker: John Shalf, MS – Lawrence Berkeley National Laboratory / Applied Mathematics and Computational Science / Department of Energy
3:10pm – 4:35pm

Heterogeneous Integration: Roundtable Discussion
Panel Session Moderator: Ravi Mahajan, PhD – Intel
Panel Session Moderator: W.R. Bill Bottoms – Third Millennium Test Solutions
Panelist: Bapi Vinnakota – Open Compute Project Foundation
Panelist: Gabriel Loh, PhD – AMD
Panelist: Jie Xue, Ph.D – Cisco
Panelist: Madhu Iyengar, PhD – Google
Panelist: Philip Wong, PhD – Stanford University
4:35pm – 4:45pm

Closing Remarks
Session Moderator: Ravi Mahajan, PhD – Intel
Session Moderator: William Chen, PhD – Heterogeneous Integration Roadmap, IEEE EPS