Member of Technical Staff ISE Labs, California, United States
Traditionally, Latch-Up testing of integrated circuits has been run on dedicated Latch-Up and ESD instrumentation. The present generation of, high pin count, high power devices are rapid outstripping the capacities of these testers. This presents an opportunity to run these Latch-Up tests on an alternative platform; ATE.
As part of the latch up test, the devices are biased to a stable and reproducible low voltage state. This can require significant amounts of current. It is also one of the areas the traditional latch-up testers are being rapidly outstripped; These testers can deliver a total of 18 Amps current. Yet we beginning to see analysis requests for devices requiring over 110 Amps on a single channel.
Even when the raw amount of power is within the testers design range, there is a question of how many power channels need biasing. Many of the devices we are seeing have a few dozen power domains and the clients would like to keep them all independent from one another. This is far beyond the current generation of latch up testers, which can only bias seven independent power domains.
Beyond the biasing issues, larger devices simply have far more pins than the current generation of latch-up testers possess. These testers are designed for up to 2304 independent pins, while we are seeing requests of devices in the 6000 pin range.
Our paper will discuss the above issues, DUT board design considerations for the ATE and present redacted data on a real world part. This will demonstrate the feasibility of running both JEDEC 78 Rev E and AEC €“ Q100-0004 Rev D latch-up testing on high power, large pin count devices, on an ATE tester. This presents a way not only to test the large, high power devices of today, but presents a way forward to test the coming generation of higher pin count, higher power devices with in-house hardware.
