This digest proposes design guidelines to reduce parasitic capacitance in planar inductor. Firstly, physics-based analytical model of parasitic capacitance in planar inductor is built in detail. Then design guidelines are derived from the variations of parasitic capacitance dependent on analytical model. In the end, FEM simulations are conducted, and seven planar inductor samples are designed and manufactured to verify proposed design guidelines, which show the effectiveness to reduce parasitic capacitance from simulation and experimental results.
