In this paper, a built-in gate driver is designed to drive a 1.7kV/1.6kA, 32-chip paralleled SiC MOSFET module. To realize the desired feature of the module, corresponding design considerations of the gate driver are discussed. Firstly, the parameters related to driving capability are figured out following a design procedure. Secondly, the delay effect in a transmission line is discussed, and a model is built to analyze the gate-to-source voltage mismatch among dies assembled at different positions. A differentiated threshold voltage strategy for arranging and selecting dies is applied to cancel mismatches. Finally, double pulse test experiments prove the feasibility of the proposed gate driver.
