Gate driver ICs are key system components to enable high efficiency and extreme power density in SMPS for Telecom, Data Center and Computing applications using the latest GaN and SiC power semiconductors..

Overall power levels have been going up in Telecom with the introduction of 5G. Likewise, power levels increased in Data Center and Computing to supply the GPUs and CPUs used in emerging applications such as Artificial Intelligence, Computer Vision, and Machine Learning. Consequently, ever-increasing power density and efficiency requirements drive adoption of GaN and SiC switch technologies in all power conversion stages, from PFC to high-voltage and low-voltage DC-DC converters. The operation of these wide-bandgap (WBG) power transistors from hundreds of kHz to MHz, combined with fast switching transients pose new challenges for the gate driving circuit, that has to ensure safe and reliable operation in these critical infrastructure applications.
In this seminar, the world’s smallest dual-channel low-side gate driver ICs will be introduced. The two new package variants (TSNP-6 and SOT23-6) associated with a strong output stage enable innovative 48 V DC-DC intermediate bus converter (IBC) topologies to achieve ultra-high power density designs in high performance computing systems. Furthermore, the high accuracy of propagation delay, allows to parallel the two outputs to double the current capability and also, to minimize dead-time losses in order to reach high system efficiency.
Galvanic isolated gate driver ICs are also key system components in order to provide basic and reinforced isolation to the high-voltage conversion stages (PFC and HV DC-DC). A new generation of dual-channel isolated gate driver ICs, with dedicated variants for GaN HEMTs and SiC MOSFETs will also be introduced in this seminar. These products are certified according to state-of-the-art component-level standards, IEC 60747-17 and VDE 0884-11, that introduce strict requirements regarding lifetime predictions of the isolation, specifying a total time-to-failure of at least 20 years. This product family brings new safety features such as dead-time control (DTC) and shoot-through protection (STP). Furthermore, faster undervoltage-lockout (UVLO) timing for quick reaction at start-up or after burst mode, results in fewer missing pulses, and robust system operation. The driver features a strong output stage with 5 A source/9 A sink capability and active output clamping, whilst VDD is still below UVLOon, to prevent shoot-through of boot-strapped half-bridges during start-up phase or after a burst mode. Multiple package variants (DSO 150mil/300mil, LGA 5x5 and 4x4) give flexibility to the system designer to choose the one that best fits the isolation requirements and target power density.
An overview of available evaluation boards and reference designs will also be given, showing the benefits at system level provided by the featured gate driver ICs. Some of these demos will be available at the Infineon booth so that the participants can have a live closer look during the tradeshow.