Increasing the switching frequency brings opportunities to reduce the size and weight of power converters. At high-frequencies, soft-switching converters are ubiquitous in adapters, datacenters, EV/HEV, and PV inverters. In optimal soft-switching conditions, it is often assumed that the energy stored in the output capacitance of power devices (Coss or Cak) is completely recovered. In the past ten years, disruptive studies evidenced the existence of an energy loss associated with Coss hysteresis due to displacement currents in the absence of channel and diode conduction.
This seminar provides in-depth coverage of Coss hysteresis losses. We will provide a background showing early experimental evidence. Also, we will show Coss losses can dominate at MHz, even when using WBG. We will describe the circuits used to test hysteresis loss in semiconductors over a vast range of voltages and frequencies (Sawyer- Tower circuit, non-linear resonance). We will discuss the physical origins Coss loss in different devices, including diodes and transistors, in Si, SiC, and GaN. We will describe how to simulate and model the Coss loss using FEA and SPICE. Lastly, we will provide insight into the JEDEC action toward standardizing testing procedures.
We expect it to interest professionals working on devices, testing and application fields.
