In the SiC cascode structure, the JFET gate resistor can effectively damp oscillations and adjust switching speed. This work investigates the effects of the JFET gate resistor on the switching process by performing PSPICE circuit simulations and proposes a novel method to control the JFET gate resistor to achieve the optimized switching performance. This method is simple and can be implemented using the miller clamp pre-driver output from a commercial off-the-shelf (COTS) gate driver. Experimental work has been done confirming the effectiveness of this approach.
