Previous research reports that the parasitic capacitance of filter inductors can result in larger capacitive currents and cause increased losses in transistors. However, previous research only discussed inductors with floating cores and frames, where the high-power and medium to high-voltage inductors are practically required to have grounded frames and cores according to the standards. To fill the gap, this paper aims to provide a comprehensive analysis of the extra switching losses caused by the parasitic capacitance of inductors with grounded cores and frames. Using the 10 kV SiC MOSFETs with an accurate digital model of the double-pulse-test (DPT) setup in LTSpice, the results imply that grounding the core and frame of inductors will cause increased transient drain current and switching losses, which are further verified in an experimental DPT results. In addition, possible solutions are proposed to reduce the extra switching losses.
