This work, for the first time, investigates the impact of the on-chip gate-ESD-protection circuit on the stability of Vth and Ron in power GaN HEMTs. An industrial GaN HEMT with such on-chip circuit shows significantly superior parametric stability compared with a commercial device without such design, under static and pulse IV tests. These long-term and short-transient stabilities attribute to the suppression of carrier trapping induced by high negative VGS(OFF) and high VDS(OFF). These results show the effectiveness of the gate-ESD-protection circuit to enhance not only gate robustness against abnormal events but also the device parametric stability in practical operations.
