In this paper, a comprehensive layout-dominated electro-thermal co-design method is derived to optimize the multichip placement pattern. The layout-dominated parasitics is established by a hybrid method of analytic approximation modeling and response surface analysis, while the layout-dominated thermal performance is evaluated by Fourier series model. Combined with the heuristic genetic algorithm optimizer, a novel successively staggered multichip layout pattern is consequently proposed and validated to achieve the current sharing and thermal balance without any additional components or advanced materials. The prototype experimental results demonstrate that the current imbalance ratio and maximum chip temperature are decreased by 50.3% and 18.1% respectively.
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