This paper presents design optimization techniques on high power-density adapters with peak power requirements. The circuit employs active Power Factor Correction (PFC), Zero-Voltage Switching (ZVS) supplying an Active-Clamp Flyback (ACF) with Gallium Nitride (GaN) primary switches, and Synchronous Rectification using a Field Effect Transistor (SR FET). This paper also discusses design challenges, such as achieving accurate voltage regulation as well as derating margin on the primary switch and SR FET, and how to address them without significant impact on efficiency.
