Modern power circuits employ high-performance switching devices like SiC and GaN MOSFET to improve power efficiency and density. These new devices are switching above 100kV/µS, and engineers must minimize the circuit\'s parasitic capacitance and inductance to control the voltage spike to ensure reliable operation. One parameter often overlooked is the total capacitance across the isolation barrier. If not well managed, the total parasitic capacitance across the isolation barrier can easily reach tens of pico Farads and resonate with the parasitic inductance to generate voltage spikes in the gate driver circuit and cause degradation to the performance of the application circuits.
