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Session: Heterogeneous Integration Paves the Way for the Future of HPC and Hyperscale Computing

Heterogeneous Integration: Roundtable Discussion

Wednesday, July 13, 2022

3:10pm – 4:35pm

Location: TechTALKS Stage, South Hall, Lower Lobby

Panel Session Moderator(s)

Ravi Mahajan, PhD

Intel Fellow, Director of Pathfinding for Assembly and Packaging Technologies for 7nm Silicon and Beyond , Technology and Manufacturing Group
Intel, Arizona, United States
WB

W.R. Bill Bottoms

Chairman
Third Millennium Test Solutions

Panelist(s)

Bapi Vinnakota

OCP Open Domain-Specific Architecture Project Lead
Open Compute Project Foundation
Gabriel Loh, PhD

Senior Fellow
AMD
Jie Xue, Ph.D

VP
Cisco, CA, United States
Madhu Iyengar, PhD

Principal Engineer
Google, California, United States
Philip Wong, PhD

Willard R. and Inez Kerr Bell Professor
Stanford University, CA, United States

Roundtable Discussion
Moderator: Ravi Mahajan, Intel Fellow, Director of Pathfinding for Assembly and Packaging Technologies for 7nm Silicon and Beyond, Technology and Manufacturing Group, Intel Corporation
Panelist 1: OCP/ODSA & Meta: Dharmesh Jani, Open Source Ecosystem Leader, Meta
Panelist 2: Chiplets Strategy: Gabriel Loh, Senior Fellow, AMD
Panelist 3: Chiplets in Photonics: Jie Xue, VP, Supply Chain Operations, Cisco
Panelist 4: HIR Roadmap: Madhu Iyengar, Principal Engineer, Google
Panelist 5: AL & ML System/Package Integration: Philip Wong, Stanford
Panelist 6: Chiplet integration: Rahul Manepalli, Intel Fellow & Director of Substrate TD Module Engineering, Intel

Round Table Panel Discussion/ Q&A from Audience