Senior Vice President Advanced Patterning, Process and Materials imec
Over the decades, as predicted by Moore’s law, the hunger for computational power has only increased. Social media, AI, Internet of Things require ever increasing amounts of computing and data storage. Initially, being a two-dimensional scaling effort driven by lithography, transistor scaling has advanced with the implementation of new devices such as the fin FET and looks to evolve further concepts such as nanosheets and CFETs. Still, lithography remains a crucial factor to simplify patterning and keep scaling economically viable.
EUV Lithography using 0.33NA full field scanners, entered production in 2019 at the 7 nm node, driven by the need to improve cycle time and cost. In the meantime, 5nm and 3nm technology have entered production, with more and more EUV layers and EUV multiple patterning. In addition to the logic foundries, DRAM memory manufacturers have started inserting EUV lithography for the same reasons.
To simplify multiple patterning below the 2 nm node reducing cost, this time for EUV-based lithography, high NA EUV lithography is under development. Besides the development of the optics and the scanner, the complete EUV ecosystem consisting of EUV materials, metrology and EUV masks need to be updated to enable a smooth insertion in high volume manufacturing.
In 2023, imec and ASML will open a high NA EUV Lab, where the first high NA scanner will be installed, together with a track and metrology systems. In this lab, the ecosystem readiness for high NA EUV will be developed and ultimately demonstrated. This presentation will demonstrate the challenges for the high NA ecosystem and provide an insight status of overcoming these obstacles.
