Vice President ,Computational Products Lam Research, California, United States
The semiconductor industry is now confronting a number of metrology and manufacturing challenges due to critical technology requirements at next-node architectures. Advanced patterning techniques, such as EUV, frequency multiplication and selective deposition, are needed to meet cost and variability challenges at smaller line dimensions. Memory technologies, such as NAND, DRAM, and others, are requiring new materials and the transition to 3D topologies that are more challenging to manufacture. Advanced logic (such as GAA architectures) and heterogenous integration are being pursued in order to reduce power, footprint, and speed in next generation devices, but also require new, higher density and more complex manufacturing techniques. These technology requirements are creating additional metrology challenges, such as a need to measure smaller dimensions in complex 3D structures, increased measurement frequencies and additional demands for metrology data integration and analysis.
In this talk, we will discuss innovative concepts to address some of these next node metrology challenges. We will review the concepts of virtual fabrication and virtual metrology, and how they can be used in conjunction with conventional metrology to better support defect analysis and yield optimization at the latest technology nodes. We will also discuss how physical metrology can be used to calibrate a virtual process model, along with how a virtual process model can be used to validate physical metrology measurements made on a 3D NAND device.
In addition, our presentation will review the concept of Equipment Intelligence®, and how sensor-based metrology is being used to improve chamber and fleet variability. We will discuss how data from in-situ and standalone metrology, using machine learning/artificial intelligence, calibrated models, and advanced analytics, can drive real-time feed-forward and feedback optimization. We will show a specific example of next-generation metrology-based optimization, by presenting an advanced, in-situ etch-depth metrology system that uses spectral analysis and machine learning to deliver significant improvements in wafer-to-wafer etch depth control.
In our conclusion, we will summarize the challenges of next node architectures, and discuss how the concepts discussed in this presentation can be used by all participants in the semiconductor technology space to measure, characterize and address these upcoming challenges.
