Over the last years, scaling and the continuation of Moore’s law has been enabled by several scaling boosters, such as self-aligned gate contacts or metal gate cut. Despite the successful integration of these new technologies, further dimensional scaling is running in saturation, where new technologies on a system level are needed in order to enable further functionality scaling. This shift to system level is often resembled to disintegration on a component level and system level integration of the individual building block. Where advanced packaging is taking one approach to integration of the system, the same applies for wafer level integration and combining different wafers, on cell level or even on transistor level. Wafer to wafer bonding provides a key technology to enable scaling on system level, where a deep understanding and influencing factors of pre and post processes are imperative to provide a successful integration process. In this presentation we want to discuss fusion and hybrid wafer bonding applications as a scaling booster for lower than 3nm nodes. We will give an overview from wafer level, down to cell and even transistor level, where wafer bonding technologies enable next generation in devices. Furthermore, essential design considerations are discussed with respect to integration process requirements.
