Vice President Engineering SCREEN, OR, United States
Wafer cleaning processes are the most used steps in microelectronic device manufacturing and an essential requirement for achieving high manufacturing yield and maximizing factory operation profitability. Wafer cleaning processes have three main requirements.
1. Remove undesirable defects (metals, particles, process residue) from the upstream step 2. Have targeted etch selectivity for all the exposed films for the process layer 3. Prepare and leave the wafer surface in the best surface state for the downstream step (Chemical Oxide, H-terminated Si etc.)
The primary goal of removing particles has seen many technology solutions implemented in fabs over the past 50 years. The early approach of undercutting and liftingoff particles using wet etching solutions was effective but as devices scaled, integrators’ tolerance for material budget loss during particle removal has now reached angstrom levels and this is no longer a viable approach.
To enhance particle removal without film loss, equipment manufactures introduced physical force components into the cleaning step to aid with defect removal. With planar device scaling, the use of sonic energy in immersion tools has been an effective approach until the technology reached its limit because the process window for particle removal, without pattern damage, disappeared from the 65nm technology node and beyond. With the introduction of Single Wafer wet cleaning tools, leading equipment manufacturers introduced dual fluid sprays which have become the dominant physical force cleaning technology used today in HVM for leading edge devices.
The trend to migrate from 2D planar structures to 3D devices with high aspect ratios and narrow line widths has again introduced challenges for device manufacturers as the process window for particle removal without structure damage or pattern collapse has narrowed. Recent developments of gate-all-around (nanosheet) devices have introduced an added challenge of how to clean surfaces that have no direct line of sight from above the wafer surface. This is driving innovation in defect-free surface preparation. Many divergent technologies are being considered to achieve high particle removal without introducing structure damage or substrate loss.
In this presentation, we will review the evolution of particle removal methods commonly used for logic and memory devices and look forward to the future of what technologies should be considered by device manufactures to support high yield in increasingly three-dimensional devices.
