Vice President ,Computational Products Lam Research, California, United States
Patterning, including lithography and other processes, is a major challenge to scaling as device manufacturers extend semiconductor development to 3nm and beyond. 193nm optical lithography with multiple patterning has been used to generate advanced features down to 7nm, but became increasingly problematic at 5nm due to the large number of patterning and process steps required at smaller feature sizes. Extreme Ultraviolet Lithography (EUV) provides a simpler, higher resolution lithography process that will allow chipmakers to pattern the most difficult features at 3nm and beyond. EUV has become the industry choice for patterning at the latest nodes, due to improved dimensional resolution and simplification of patterning and processing.
Unfortunately, transitioning to EUV lithographic exposure is likely insufficient on its own. Patterning specifications are extraordinarily challenging at 3 nm, with processes that approach the boundaries of physics. Yield can be impacted by unwanted variations and stochastic-induced defects during EUV processing, creating unintentional line edge roughness (LER), line width roughness (LWR) and edge placement error (EPE). Compounding these issues, lithography, patterning, and downstream processes must be co-optimized to have an acceptable yield and cost outcome.
During this seminar, we will discuss holistic patterning and co-optimized integration schemes that can decrease variability and defects, while minimizing patterning and processing costs. We will review the challenges discovered in earlier node transitions, along with the future roles of predictive process modeling, variability control, material optimization and tool control on next-generation scaling efforts. We will specifically discuss “scaling boosters” such as advanced EUV resists, and how advanced lithography will need to be combined with materials engineering to improve patterning control and lower stochastic-induced defects. The presentation will conclude by discussing the future of DTCO and material optimization on devices at the 3nm node and beyond.
