Principal Engineer Samsung Display Yongin, Republic of Korea
Compared to the conventional clock-forwarded scheme (MIPI D-PHY) for display data transmission in mobile product, we propose a high-speed clock embedded interface for advanced mobile display driving architecture. To achieve a MIPI compatible interface protocol, we suggest a perturbation-minimized D-PHY operation. Furthermore, we propose a novel fast wake-up CDR architecture to mitigate the intrinsic drawback comes from clock/training overhead. We demonstrate that our mass-producible system successfully operates at 6.0Gbps with fully verified MIPI compatible features.
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